Bistable circuit



Marh 8 1960 c. M. CAMPBELL, JR 2,928,010

BISTABLE` CIRCUIT Filed Feb. 20. 1958 l g 46 a INVENTOR.

HGENT United States "ice BISTABLE CIRCUIT Carl M. Campbell, Jr., Bryn Mawr, Pa.,.assignor to Burroughs Corporation, Detroit, Mich., a corporation of Michigan Application February 20, 1958, Serial No. 716,470

' 1'2 claims. (C1. .w1-sexs) 'The present 'invention' relates to bistable electronic circuits and more particularly to bistable electronic circuits having set and reset facilities and which switch rapidly from one stable state to the other.

Bistable circuits, often referred to as flip-flop circuits, are widely used in the counting or trigger circuits found in electronic computers. In these and other uses it is often desirable to have a bistable circuit with two signal input points and which can be made to assume a selected one of the stable conditions. Many prior art bistable circuits utilizing transistors have required a large number of circuit components to provide this capability of assuming a given one of its-stable conditions, referred to as a set and reset capability. In addition, in many prior vart bistable circuitsutilizing transistors the transistors must be saturated, and hence a relatively long time interval is required for the circuit to change from onev stable condition to the other-as a result of `the base storage time associatedwith saturated transistors. This may be disadvan tageous in high speed Work.

lf the particular ip-op circuit is to be controlled by means of and or orV gates, asis common in electronic computers, it is usually necessary to incorporate a number of external circuit components to accomplish the gating function. In the circuit of the present invention the gating functions are readily accomplished by a minimum number of components whichV are made an integral part of the iiip-i'lop circuit. v

Accordingly,it is an object of the present invention to provide an improved bistable electronic circuit utilizing semiconductor amplifier devices such as transistors.

Another object ofthe present invention is ltoprovide a bistable transistor circuit utilizing a small number of components to provide ,set and reset capability. ,l j

A further object of thepresent invention is to provide a set and reset bistable circuit utilizing transistors in a circuit arrangement which materially decreases the time required for the circuit to change from one stable condi- '.tion to the other.

Still another object of the present invention is to prowide a bistable transistor circuit having set and reset capability controlled b y internal gating means.l

In accordance with the present invention a rst tran- :s'istor of one conductivity ,type has its emitter-collector circuit connected directly to the emitter-collector circuit of a second transistor of conductivity type opposite to that of the first. An impedanceelement connectedto the junction point of the two emitter-collector circuits serves as a common load element for the two transistors in a manner such that current flow through the second transistor and the impedance element prevents or inhibits conduction of the first transistor. A third transistor having its control electrode coupled with the emitter-collectorV circuit of the first transistor, and hence .its Vstate of conduction controlled by the current ow through the emittercollector circuit of the rst transistor, has its emitter-collectorcircuit connected in series arrangement with the emitter-collector circuit of the second transistor. AA sec- 2,928,910 PatentedMar. 8, 1966 ond impedance element connected to the junction point of theernitter-collector circuits of the second and third transistors serves 'as a common load element for the second and'third transistors in a manner such that current flow through the impedance element and the third transistor provides a voltage upon the second transistor of suiiicient magnitude to maintain the second transistor nonconductive during conduction of the third transistor. Thus, the circuit has onel stable condition wherein the first land third transistors are conductive and another stable condition wherein the second transistor is conductive.

When the circuit is in its first stable condition with the tirst andthird transistors'conducting, a set pulse or signal applied to the control electrode of the first transistor changes the circuit to the second of its stable conditions with `only the second Ytransistor ina conductive state. Thereafter the repeated application of signals to the control electrode of the rst transistor has no effect upon the circuit.

To provide the reset capability a fourth transistor is included in the circuit with its emitter-collectory circuit connected in parallel withthe emitter-collector circuit of the third transistor. Thus the impedance element lwhich isi common to the emitter-collector circuits of the second and third transistors is also common to the emitter-collector circuit of the fourth transistor. Hence, the application of a reset control signal to the control electrode of the fourth transistor during the time that the second transistor is conductive will render the fourth transistor conductive and thereby increase the current flow through the second impedance element. This renders the second transistor nonconductive and thereby permits the rst transistor to assume its original conducting condition. y

ln another embodiment of the present invention the emitter-collector circuit of a fth transistor is connected in parallel with that of the fourth transistor to provide an "or gate cap-ability on the reset Likewise another transistor is connected inparallel with the rst transistor to provide an and capability on the se manner the gating functions are controlled by a minimum number of additional circuit elements which are made an integral part of the bistable circuit.

The novel features of the present invention are set forth in the appended claims. The invention itself, however, both as to its organization and method of operation, as well as additional advantages and objects thereof, will be more clearly understood from the following descrip- Vtion when read in conjunction with the accompanying drawing wherein like components bear the same reference numeral throughout, and in which, Y

Fig. 1 is a schematic circuit diagram illustrating a preferred embodiment of the bistable transistor circuit provided in accordance with the present invention, and

Fig. 2 is a schematic circuit diagram of a bistable circuit provided in accordance with the present invention which incorporates an internal gating arrangement. I

In Fig. l an NPN junction transistor 10 having a base electrode 411, an emitter electrode 12, and a collector electrode 13 together with three PNP junction transistors 20, 30, and 40, having base electrodes 21, 31, and 41, emitter electrodes 22, 32, and `42, and" collector electrodes 23, 33, and 43, respectively, are included in a preferred embodiment of the bistable circuit of the present invention. Although the circuit diagram illustrated in Fig. 1 incorporates specific conductivity type transistors, it is to -be expressly understood that the types shown are for purpose of illustration only and are not to be taken as limitations of the present invention.

The collector electrode 23 of the second transistor 20 is connected directly to the emitter electrode 12 of the j first' transistor 10 providing a common junction point 45 to which yis connected a first impedance element such In this as a resistor 46 which is also. connected to the negative terminal of a nrstrsource of direct current (D.C..) potential illustrated as a battery 47 having its positive terminal connected to a point of fixed reference potential referre'd to as ground. The resistor 46 and battery ,47 may advantageously be so selected that a substantially'l constant current source is provided to avoid'transisto'r saturation. The emitter electrode 2?. ofV the second transistor 2t? is coupled by means of a second impedance element such as a resistor S6 with the positive terminal or a second source of D C. potential illustrated as a battery 57 having its negative terminal grounded; The base electrode 21 of the second transistor 20 is connected to a point of fixed potential illustrated as being provided by a third battery' having its negative termi` nal grounded. The magnitudes of the potentials provided by the various sources of D.C. potential illustrated in the drawing will be more vfully explained at a later time.

v The base electrode 31 of the third transistor V30 i's connected to the collector electrode 13 of the iirst transistor 16,5 at a common junction point 55 which is in turn coupled through a dropping resistor 66 to a point of positive lpotential provided by a fourth source of 'potential illustrated as 'a battery 77 having its'negative terrninal grounded. The vemitter electrode 32 'of the -thir'd transistor 3i) is connected directly to the emitter electrode 42 'of the fourth transistor "4h and'also to the emitter electrode 22 of the second transistor. Hence, 'the second impedance element illustrated as a resistor 56 is common to the emitter-collector circuits vlof 'the second, third, and fourth transistors, andr'together with :the lbattery 57 may advantageously vbe adapted lto lserve `as "a constant current source. The'ollector lelectrode 33 and t3 of-the third and :fourth transistors are -dir'ectly'interconnected and 'also coupled through Malseconddropping resistor "76 to Aa negative potential provided "by-af'rth source lof DLC. potentialillustrated as a `battery 87 inavingits positiveterminal connected toiground.

Asset forth above 4the impedance of the resistors 46 and "56 andthe voltages of the'potential supplies 47 and 57 maybe'so selected that constant Vcurrent 'sources are provided in Aa manner such that saturation of the various transistors is prevented. To further -insure nonsaturation ofthe transistor V20, V`a diode l48 having 'its 'anode connected to the emitter-12 Vand itscathodegrounde'd may bel inelu'dedlin theci'rcuit to limit the potential upon the emitterlfz to 'values which are never morepositivc thanground. vAs illustrated 'in 'the drawing, lthe base electrode 11 of the first transistor it) isidentiiied sia set signal input point, and the base 'electrode V41 of the'fourth transistor '40 is identied Aas a reset 'signal `input point. lThus the base electrodes 11 and 41'are to be coupled with vsignal 'sources'which'provide negative going control signals. The emitter 12 of transistor 10 is clamped tothe `rnegative potential provided by 'a battery 59 having its positive terminal grounded, by means 'ot'fa vclamping diode 58 which has its cathode connected n to the emitter 12jand its anode connected to potential source 59. The base of transistor 11 is maintained 'positive with respect to the potential of battery 59 inthe absenceV of a'negative going control'signal, and negative With respect to the potential of battery-59m"response to a control signal. In 'a similar manner the potential of the basedl is normally positive'with 'respect'to the potential of battery 67 in the absence of a reset 'signal and becomesnegative lwith respect to battery' 67 during the'occurrence of a reset signal.

To further illustrate with vmore' particularity thefjoperation of the bistable tcircuiti 'of `Fig. l, aparticulariset of values for thel voltages of the varioussourcesfolY i LC. potential are Yincluded in parentheses adjacent -'to "their respective sources. It is to be expressly underst'ood'that the particular valuesshovvn' are only for purpose yoffillustration, 'andiit 'is to be'fur'theridersoodthafltliogha pluralityY of voltage sources are illustrated to facilitate the explanation and vteachings of the .operation of the present invention, only one source of potential having various voltage taps thereon would be required.

As set -forth above, in the absence off any input signal to the circuit the first transistor tends to conduct as a result of the base 11 being .maintained at a potential which is more positive than the emitter 12 providing the transistor 2t) does ino't conduct and iraise the potential at point 45 to ground. The potential difference between the voltage source v'57 and the voltage sources 67 Vand 77 is such that 'the 'einitterlbase junctions of the transistors 20 and Sortend to be forwardly biased. However t'he impedance of Ythe resistor `56 and 4poteutialtof -battery 57 are so selected that the current owing through resistor 516 as a result of 'one 'of said transistors 2G or 3@ being conductive serves to maintain the other nonconductive. That is, as soon as one transistor conducts its emitter potential Ifollows lits base potential. Since the emitters 2.2, 32, and 42 yare *always at equal potentials, the transistor with the lower -ba'sefpotential will be conductive.

lLfrss-umiingthe initial Vcondition of the circuit lto be that in `which .'the rst transistor 1d is conductive, the current now from'the potential source y77 'through the dropping resistorot 'and .the collector-emitter "circuit of 'the irst "transistor 'te causes l-th'e'potential of th'e'basel of the third Vtransistor Se to become negative `'tvitlilrespect to Ltheftixed Ypotential upon the baseof thefsecond transistor 12h. Hence, the third'transistor 30 is vrendered conductive causing current to flow through the resistor thereby ycr'eatinga potential drop sunicient to-maintre-emitter 2st-of -theisecon'd :transistor 20 negative with resp-ect 1n die `potential maintained by eine third source oitDlCjpotentifal lj'upon the base Q21. vlf-husth'e second 'transistor zo -is maintained -norrconducriv-e.

The fniagnitude of the vv'atrilcnis impedance --elenrents and the amplitude of the D.C.-'pot`entialsis'=so selected that iv'hentlic iirs't transistor '10 is Conducting the base of the-third transistor "Solis V'more negative*thanthebase 'ofth'e `ifourth transistor 40. Hence, thefourth transistor ditremains norrnally nonconductive.

When-ainegative fset `signaliis-ipplit-d'to the base of'l'tlierir transistor 1Q'to'placetliebascllemore negative 'thanlbattery 59' the' emitter `will vftfyto follow'the l'base but will be clamped to the potential of battery 59,'-and y vl'tt'tl'iti's*becomesnonconductivc. 'lf'h'is'causes ll'e'c rpoteritia'l to'rise-tothe` positivevoltagel `of the r'potential 77,'therebyrising'the base potential firewire; @assister-salatura are bssefpstemiai nof the scndtriinsistori-ZG. Asthe' base of the third 'transistor becomes morepositivethelemitters '22 and "32 become 'more 1'J`osi'tiv'e 'until-a`l condition'is'established'such that the ase junction of the' second transistor is more'for- 3 ised than that of the third transistor. "Hence, the 'seeondtransistor is Irendered"'condnctive, With 'the current flow through the resistor 56 maintaining Lthe `emitter-base junctinfof thethird transistor 3'0'backvvardly biased. The value of the `impedance elements and of the 'voltage supplies is advantageouslyl 'selectedmtoprovide 'rapidV switch- 'iirgtbugt preventsaturtion 'of 'the transistors.

"Asmtlie'sec'ond transistor v'20' conducts, .its emitter-co1- lector current tiovvs' through the resistor '46 whichsisfcoml*mon `to-'the einitterlcolleetor circuits ofthe irstfand second tran-sisters. vThus ther junction'145fof the 'collector-23 and the iemitter v'12* of 'the-iseeondfandvthirdtransistors, respectively, is `raised ftoea potential .such 'that'the emitterbase unctionfof'theersttransistor :becomes-backwardly bias' toifthe'fextent that removal lbf he:serifsigal 90 fourth transistor.

` apriamo t `eonductive since its base isiiormally more positiveY than that of transistor 20.

The circuit will then remain in its second stable condition until a negative going-reset signal 91 is applied to thebase of the fourth transistor 40 to make its base more negative than Vthat of transistor 20, rendering the fourth transistor conductive. When the emitter-base junction of the fourth transistor is thus forwardly biased the current passing through the load resistor 56 switches from transistor 20 to transistor 40. Hence, the second transistor 20 becomes nonconductive permitting the junction 45 between the collector and the emitter of the second and iirst transistors to become more negative. As soon as the junction 45 reaches a potential which is negative with respect to the quiescent voltage maintained upon the base 11 ofthe iirst transistor 10, the first transistor is rendered conductive. When the irst transistor becomes conductive current flow through the dropping resistor`66 causesv the base 31 of the third transistor to againbecome negative with respect to the quiescent voltage of the base 41 of the Thus when the reset signal 91 is removed from the base 41, the fourth transistor is rendered nonconductive and the third transistor is rendered conductive. The conduction of the third transistor 30 and the resultant current ow through resistor 56 serves to. maintain the emitter-base junction of the second transistor 20 backwardly biased, and thereby place the circuit in its iirst stable condition.

Output signals from the circuit canof course be derived I from various points, and thus for purpose of illustration a first signal output terminal A is connected to the collector 'end of the resistor 76, and a second signal output terminal B is connected to the collector end of the resistor 66. Thus a signal is provided at the signal output terminal A which has a potential equal to that of the battery 87'when the second transistor 20 is conducting, and a more positive potential during the time that the first and third transistors'10 and 30 are conducting.l In like manner the potential of the signal provided at the second signal output terminal B varies from a positive potential equal to that of the battery 77 when the second transistor is conducting to a more negative potential during conduction of the first and third transistors. Thus it is seen that the bistable circuit of the present invention provides positive and negative going output signals and hence can serve lto control either NPN or PNP transistorswhich might bev coupled with the signal output terminals.`

In Fig. 2 a further embodiment of the present invention I is illustrated which is similar to the circuit of Fig. l, but

includes an additional PNP transistor 50 and an additionalA NPN transistor 60 to provide or and and gating arrangements in a manner such that the gating circuits are internal to the bistable circuit. The sixth transistor 60 has an'emitter electrode 62 connected to the emitter 12 of the first transistor, and a collector electrode 63 connected to y,the collector 13 of the iirst transistor. Thus the emitter- .collector circuits of the first and sixth transistors are con- ;nected in parallel. In a similar manner the fifth tranesistor 50 has an emitter electrode 52 connected to the emitter 42 of the fourth transistor, and a collector electrode 53 connected to the collector 43 of the fourth tranfsistor. Hence the emitter-collector circuits of the fourth and iifth transistors are connected in parallel.

The sixth transistor 60 has a base electrode 61 which is maintained at a potential corresponding to the potential` To change the cir 3 0 are conductive to the condition where the secondtras; sistor 20 is conductive,'the iirst transistor 10 andthe sixth. transistor 60 must be prevented from conducting bytthe simultaneous application of negative going signals to their respective control electrodes. Thus an internal andwg'ateis providedfor the bistable circuit ofthe present invention. I

. The ifthtransistor 50 has a base electrode v51 which is maintained at a potential sufficiently positive with respect to the potential of theemitter 52 to render the fifth transistor normally nonconductive in the absence of input signals to the base electrode. Thus when the second tran-l sistor 20 is the only conductingtransistor in the bistable.,

circuit, the application of a negative signal to the base electrode of either the fourth transistor or to the base electrode of the transistor S0 to render the fourth or viifth transistor conductive Will switch the current flow through the vresistor 56 and transistor 20 to transistor 40. or 50,

thereby rendering the second'transistor 20 nonconductive. l

Although the resistance of the various impedance elements may be varied in accordance with the particular use of the bistable circuit, the following values for the circuit of Fig. l are listed by `way of example, the'particular resistances having been selected for use in conjunction with the voltages illustratedin parentheses in Fig. l in a manner such that suiiicient current is provided for proper circuit operation but'A an insufficient amount for transistor saturation.

Resistor 46 4750 Resistor 56 3400 Resistor 66 499i Resistor 76 357' In the circuit diagrams illustrated in Figs. l and 2,

particularly conductivity type transistors are shown in an,

, ous points of potential and also a reversal of the clamping` diodes.

There has thus been disclosed a bistable circuit having set and reset capability and which requires a minimum amount of time to change from one stable condition Y to the other. In addition, the bistable circuit provided in accordance with the present invention accommodates internal gating arrangements in ai simplified manner which makes it particularly adaptable for use in high speed computing or counting circuitry.

What is claimed is:

1.` A bistable circuit comprising in combination: first and second transistors of opposite conductivity type each having a base, an emitter, and a collector; a rst resistive impedance element having one termina-l connected to they collector of said first transistor and to the emitter of said second transistor; a third transistor having a control electrode connected to the collector of said second transistor and a load circuit including a second resistive impedance element; and means including a source of potential connected to the other terminal of said iirst impedance element and to each of said transistors rendering said second transistor nonconductivein response to voltages'across said iirst impedance element associated with current flow through said first transistor andy rendering said rst transistor nonconductive in response to voltages across said second impedance element associated with current flow through said load circuit. 1

l2. A bistable circuit comprising in combination, first and second semiconductor signal translating devices of opposite conductivity type each having a base, an emitter; and a collector, a iirst resistor having one terminal con-f nected to the emitter of said first device and to the co1-. lector 'of said second device, voltage clamping means conne'cte'd to the emitter of said first device, bias means coupled with said devices Aand said resistor for rendering the state of conduction of said first device responslve to the voltage across said resistor associated with lcurrent dow through said second device, a third semiconductor signal translating device having a control electrode coupled with the collector of said first device and an emitter-collector circuit connected to the emitter of said second device, a second resistor having one terminal connected to a source of potential and another terminal connected to the emitter-collector circuit of said 'third device and to the emitter of said second device rendering the state of conduction of said second device responsive to the voltage across said second Vresistor associated with current flow through the emitter-collector circuit 'vof said third device, and means including a fourth semiconductor signal translating device coupled with said second Vresistor adapted to selectively render said second device nonconductive in response to control signals.

3. A bistable circuit comprising in combination, first and second transistors of opposite conductivity type each having base, emitter and collector electrodes, a first resistive impedance element having one terminal connected to the emitter electrodeV of said first transistor and to the collector electrode of said second transistor, a second resistive impedance element having one terminal connected to the collector electrode of said first transistor, a third resistive impedance elevent having one terminal connected to the emitter electrode of said second transistor, voltage limiting means connected to the -emitter of said first transistor, a third transistor having a Ybase e1ectrede coupled to the collector electrode of said first transistor and an emitter-collector circuit coupled to said one electrode of said third impedance element, a fourth transistor having an emittercollector circuit coupled to said one electrode of said third impedance lelement and a control electrode adapted to have control signals applied thereto, means including a source of potential coupled Witheach of said transistors and with the other terminal of each of said impedance elements adapted to render said first transistor nonconductive in response to current flow common to said second transistor and said first impedance element and to render said second transistor nonconductive in response to current flow common to said third transistor and 'said third impedance element, and signal input means coupled with lthe base of said first transistor and the control electrode of said fourth transistor.

4. A bistable 'circuit comprising: first and second transistors of one conductivity 'type and a third transistor of another conductivity type, each of said transistors having a -base electrode, an emitter electrode, and a collector electrode; a first resistor having one terminal connected to a source of potential and another terminal connected tothe` collectorelectrode of said first transistor and to'the emitter'electrode of said third transistor adapted to providelaiirst signal in 'response to conduction of said first transistor; means rendering said third transistor non'conductive duringsaid first-signal and conductive in the absence of said first signal; means including a second resistorri'having one terminal connected to a source of potential vand another terminal connected to the lbase'electr'o'de 'ofsaid second transistor and to the collector 'electrode of said third transistor 'adapted to maintain'said second transistor conductive only during conduction AofV said`third-transistor;'a third resistor having one terminal connected to `a "source of Vpotential and another terminal connected lto 'the temitter 'electrodes of said first `and second ltransistors adapted Vto provide `a 'second :signal during c'onduction of said -second transistor; 'means `rendering said first transistor nonconductive in V'response to said sec'on'd signal and 'conductive-in the absence of said second'si'gnal;land'signal-input circuit means coupled With saidfirst Tand hird transistors.

5. A bistable circuit comprising: first, second, .and

third transistors of one conductivity type each having'a base, an emitter, and a collector; a fourth transistor'of4 another conductivity type having an emitter connected'to the collector of said first transistor, a collector connected to the vbase of. said' second transistor, and a baseya first resistor connected to Vthe emitter of said fourth trans sistor; a Vsecond resistor having yone terminal connected to the emitters of said first, second, and .third transistors;l

a third resistor connected to the collector of said fourth' transistor; means connecting the collector of said second transistor to the collector of said third transistor; and

means Vincluding a source of potential connected to each of 'said resistors maintaining said first and fourth transistors in opposite states of conduction and adapted to: prevent saturation of said transistors.

6. A bistable circuit as defined in claim 5 and including a fifth transistor of the same conductivity type as said third transistor and having an emitter-connected to the.

emitter of said third transistor, a collector connected to the collector of said third transistor, and a control electrode adapted to receive control signals.

7. A vbistable circuit as defined in claim 5 and including.

a fifth transistor of the same conductivity type as said fourth 'transistor and having an emitter connected ,to the.

emitter of said fourth transistor, a collector connected to the lcollector of said fourth transistor, and a control electrode adapted to receive control signals.

8. A bistable circuit as defined in claim 7 and including a sixth transistor of the same conductivity type as said third transistor and having an emitter connected to thev emitter of said third transistor, a collector connected to the collector of said third transistor, and a control electrode adapted to receive cont-rol signals.

9. A bistable circuit having set and .reset Vcapability utilizing transistors operated in their non-saturated regions of operation comprising in combination, first and second transistors of opposite conductivity type each having base, emitter, and collector electrodes, means including.

a first resistor having one terminal connected to a .source of potential and another terminal connected to the collector elcctrode of said first transistor and to the emitter electrode of said second transistor adapted to maintain said second transistor nonconductive during conduction.

of said 'first transistor, voltage clamping means connected to the collector electrode of said first transistor, .a .third transistor of conductivity type opposite that of the .second transistor having a .base electrode connected to the collector electrode of said'second transistor-and anemitter electrode connected to the emitter electrode .of vsaid first transistor, means including a second resistor having one terminal connected to a source ofpotentia'l and another terminal connected to the emitter electrodes of saidfirst and third transistors adapted to maintain .saidfirst and third transistors in opposite states of conduction, va fourth.

transistor having an emitter-collector circuit connected .to the emitter electrode of said first transistor and .a control electrode .adapted to receive control signals, .means including said second resistor rendering saidfirst transistor nonconductive in response to conduction or" .said fourth electrode,.an emitter electrode, and a cllector-.electrode;. a first resistor connected between a 'first .point of fixed potential and the emitterelectrodes of each .ofsaidBNP transistors; a second .resistor connected .between -.a .second point of fixed potential and the .emitter electrode of said fourth transistor; circuit means `providing a .direct acurrent path between the collector electrode of said rst transistor and the emitter electrode of said fourth transistor and the base electrode of said second transistor;

voltage limiting means connected to the emitter of said fourth transistor; and means connected to the base electrodes of said rst, third, and fourth transistors maintaining the base of said first transistor at a xed potential, the base of said fourth transistor at a potential which is constant in the absence of said first signal, and the base of said third transistor at a potential which is constant in the absence of said second signal.

11. A bistable circuit as dened in claim 10 and including an additional PNP transistor having a control l0 electrode adapted to receive input signals and an emittercollector circuit connected to said rst resistor.

12. A bistable circuit as defined in claim 11 and including an additional NPN transistor having a collector electrodeconnected to said third resistor, a control elec-v trode adapted to receive input signals, and an emitter electrode connected to said second resistor.

References Cited inthe file of this patent UNITED STATES PATENTS v 2,663,800 Herzog Dec. 22, 1953 2,744,198 Raisbeck May 1, 1956 2,770,732 Chong Nov. 13, 1956 2,820,155 -Linvil1e 'Jan. 14, 1958 2,827,574 Schneider Mar. 18, 1958 Y 

